Semiconductor device, wiring substrate, and method for manufacturing wiring substrate

ABSTRACT

The reliabilities of a wiring substrate and a semiconductor apparatus are improved by reducing the internal stress caused by the difference of thermal expansion coefficients between a base substrate and a semiconductor chip. A wiring layer ( 5 ) is provided on one surface of a silicon base ( 3 ). An electrode as the uppermost layer of the wiring layer ( 5 ) is provided with an external bonding bump ( 7 ). A through-electrode ( 4 ) is formed in the base ( 3 ) for electrically connecting the wiring layer ( 5 ) and an electrode terminal. The electrode terminal on the chip mounting surface is bonded to an electrode terminal of a semiconductor chip ( 1 ) by an internal bonding bump ( 6 ). The thermal expansion coefficient of the silicon base ( 3 ) is equivalent to that of the semiconductor chip ( 1 ) and not more than that of the wiring layer ( 5 ).

FIELD OF THE INVENTION

The present invention relates to a semiconductor apparatus, a wiringsubstrate for the semiconductor apparatus and a method for manufacturingthe wiring substrate, and, more particularly to a Flip-Chip typesemiconductor apparatus which is a face-down type, the wiring substratefor the Flip-Chip type semiconductor apparatus and a manufacturingmethod for the wiring substrate.

BACKGROUND OF THE INVENTION

All of patents, patent applications, patent publications, scientificarticles and the like, which will hereinafter be cited or identified inthe present application, will hereby be incorporated by references intheir entirety in order to describe more fully the state of the art, towhich the present invention pertains.

Recently, for improving mounting density of a semiconductor package,shrinkage, miniaturization, and pin-multiplication of the package hasbeen progressed. Aligning electrode terminal in the area is an effectivetechnology against the shrinkage and pin-multiplication, whilemaintaining a wide pitch between electrode terminals. In the secondmounting for bonding the semiconductor package and a motherboard, thistechnology means a Ball Grid Array type of semiconductor packagingtechnology which bonds the electrode to the motherboard with solderbumps arranged on an interposer substrate. On the other hand, in thefirst mounting for bonding a semiconductor chip and the interposersubstrate, this means a Flip-Chip bonding technology for bonding theboth by area aligning, for example, the solder bumps or gold bumps on afunctional surface of the semiconductor chip.

FIG. 1 is a cross sectional view showing a structure of conventionalsemiconductor apparatus. A semiconductor apparatus, which uses thepackaging technology like the above and the Flip-Chip bondingtechnology, is a Flip-Chip Ball Grid Array (FCBGA) shown in FIG. 1. Thishas advantages for the shrinkage, miniaturization, andpin-multiplication of the package, as well as having a low wiringresistance compared with a wire bonding type of semiconductor packagewhich bonds the semiconductor chip and the interposer substrate with agold wire, thereby suitable for high speed operation. Therefore, anincrease of the technology application is being expected. A material ofthe interposer substrate is divided into a resin material and a ceramicmaterial. The resin material having advantages in manufacturing cost andin electrical characteristics has been mainly used. An example using theFlip-Chip bonding technology has been disclosed in Japanese Laid-OpenPatent Publication No. 08-167630, in which a structure forming a wiringin a polymer material having a low thermal expansion coefficient closeto that of silicon, and bonding a chip and the wiring with athrough-hole is shown. Since a mounting area of this structure isdecreased compared with the wire bonding, as well as shortening abonding distance, and by using a material having a thermal expansioncoefficient close to that of silicon, a thermal stress is also relaxed.

Up to now, a development of LSI has been carried out based on a scalingrule, in which if a dimension of a transistor is shrunk by 1/k, thedensity of the LSI becomes k2 times and an operation speed becomes ktimes. With a progress of the shrinkage and a demand for high speedoperation, so-called, RC delay due to increase in a wiring resistance(R) and a capacitance (C) between wirings (hereinafter, referred to aswiring capacitance) has become not negligible. Therefore, employments ofCu as a wiring material for decreasing the wiring resistance and a lowdielectric film (Low-k film) for an interlayer dielectric film fordecreasing the wiring capacitance are supposed to be promising. Inaddition, for stable operation of LSI at high frequency region, astabilization of power voltage and an arrangement of decouplingcapacitor against a high frequency noise are essential. Therefore, acapacitor apparatus, which has a large capacitance formed on a siliconhaving a through-hole, or on a substrate composed of insulating filmcontaining silicon, or on a sapphire substrate, and a module mountingthe capacitor apparatus have been proposed. This is disclosed inJapanese Laid-Open Patent Publication No. 2002-008942.

In addition, because of high-scale integration of LSI and progress ofpin-multiplication due to development of System-On-Chip technologyconfiguring a system by forming, for example, various functionalelements and memories on a single chip, a semiconductor chip still has atendency to grow in size even after compensating contribution of theshrinkage and miniaturization by the electrode area alignment of theFlip-Chip.

However, according to the conventional technology, in the structure ofFlip-Chip type of semiconductor apparatus shown in FIG. 1, when a resinsubstrate is used for the interposer substrate, a linear expansioncoefficient of the resin substrate is around 15 ppm/C in contract with2.6 ppm/C of that of semiconductor chip of which base material is mainlysilicon. The difference is large, thereby causing a large internalstress within the semiconductor apparatus by the difference of thermalexpansion coefficient between them. Currently, the reliability of thesemiconductor apparatus is maintained by filling a resin in a space atbonding part between the semiconductor chip and the interposersubstrate. However, by increase in internal stress due to growing insize of semiconductor chip according to increase of the number ofexternal terminal in a future, it is predicted to become difficult tomaintain the reliability. In the above-described Japanese Laid-OpenPatent Publication No. 2002-008942, the semiconductor chip is bonded onan organic layer forming a capacitor. Then, the issue of thermal stressconcentration due to the difference of the expansion coefficient has notbeen solved. In addition, including the bonding structure disclosed inJapanese Laid-Open Patent Publication No. 167630, the reliability ofpackage mounted on the interposer substrate, of which thermal expansioncoefficient is matched to that of silicon, is decreased due to aninternal stress caused by the difference of thermal expansioncoefficient when the package is mounted on a motherboard.

Furthermore, a dielectric constant of Low-k film, which is beingsupposed to be applied as a countermeasure for the RC delay, isdecreased by doping, for example, fluorine, hydrogen, and organics in asilicon oxide (SiO2) film, or making the material porous. Then, it iswell known that the Low-k film is fragile compared with a conventionalinterlayer dielectric film such as silicon oxide film. This means adecrease in allowable limit of the internal stress caused by thedifference of linear expansion coefficient between the semiconductorchip and the interposer substrate, and may cause a reliability issuewhen the shrinkage and pin-multiplication are further progressed in afuture.

Moreover, recently, there is a tendency to replace a Tin-Lead solder,which has conventionally been used so far for the solder material, witha Lead-free solder. Electronics industries have a plan to abolishcompletely a solder containing Lead. The Lead-free solder, in which Tinis a base material, has a substantially small stress relaxation effectcompared with the Tin-Lead solder, which has a stress relaxation effectto decrease a stress generated at the bonding part through compositionchange of solder itself. Accordingly, the internal stress increases, andmay cause a reliability issue when the shrinkage and pin-multiplicationare further progressed in a future.

DISCLOSURE OF THE INVENTION

It is therefore an object of the present invention to provide asemiconductor apparatus which is free from the above issues.

It is another object of the present invention to provide a semiconductorapparatus, in which an internal stress caused by the difference ofthermal expansion coefficients in a wiring substrate is decreased,thereby increasing the reliability and capable of responding to furthershrinkage and pin-multiplication.

It is a further object of the present invention to provide a wiringsubstrate of semiconductor apparatus which is free from the aboveissues.

It is a still further object of the present invention to provide awiring substrate of semiconductor apparatus, in which an internal stresscaused by the difference of thermal expansion coefficients in a wiringsubstrate is decreased, thereby increasing the reliability and capableof responding to further shrinkage and pin-multiplication.

It is a yet further object of the present invention to provide a methodfor manufacturing a wiring substrate of semiconductor apparatus which isfree from the above issues.

It is an additional object of the present invention to provide a methodfor manufacturing a wiring substrate of semiconductor apparatus, inwhich an internal stress caused by the difference of thermal expansioncoefficients in a wiring substrate is decreased, thereby increasing thereliability and capable of responding to further shrinkage andpin-multiplication.

According to a first aspect of the present invention, the presentinvention provides a semiconductor apparatus in which a semiconductorchip is mounted on a wiring substrate with Flip-Chip, wherein the wiringsubstrate comprising: a base substrate; a wiring layer having aninsulating layer and a wiring formed on a wiring layer formation surfacewhich is one surface of the base substrate; an electrode formed on achip mounting surface which is a backside of the wiring layer formationsurface of the base substrate; and a through-electrode formed on thebase substrate electrically connecting the wiring layer formed on thewiring layer formation surface and the electrode formed on the chipmounting surface, wherein a thermal expansion coefficient of the basesubstrate is equal to a thermal expansion coefficient of thesemiconductor chip, or less than a thermal expansion coefficient of thewiring layer, wherein the semiconductor chip is bonded to the chipmounting surface with face-down. In addition, it is favorable that thethermal expansion coefficient of the semiconductor chip is smaller thanthat of the wiring layer.

With the present configuration, since the semiconductor chip is mountedon the base substrate of the wiring substrate, the difference of thermalexpansion between the semiconductor chip and the base substrate issuppressed. Therefore, a bonding reliability between the semiconductorchip and the wiring substrate is improved. When the presentconfiguration is mounted on a motherboard substrate, since the wiringlayer of the wiring substrate faces to the motherboard substrate and thewiring layer thereof exists between the motherboard substrate and thebase substrate, a stress of the wiring layer caused by the difference ofthermal expansion between the motherboard substrate and the basesubstrate can be relaxed, thereby resulting in increase of electricbonding reliability. In the explanation, a motherboard was used as anexample for explaining a substrate on which the wiring substrate of thepresent invention is mounted, but not limited to the motherboard. Anysubstrate, on which the wiring substrate of the present invention ismounted and which is different from the base substrate, may be possible.In the present embodiment, a support means a substrate which isdifferent from the base substrate, and on which the wiring substrate ofthe present invention is mounted.

The base substrate may be any one of a silicon, a ceramic, and aphotosensitive glass.

A reinforcing frame may be stuck at least on a part of outer part of thechip mounting position of the chip mounting surface. In addition, it isfavorable that the thermal expansion coefficient of the reinforcingframe is equal to the thermal expansion coefficient of the semiconductorchip, or less than that of the wiring layer.

A thickness of the base substrate, at least one part of outer part ofthe semiconductor chip mounting position at the chip mounting surface,may be thicker than the other part of the semiconductor chip mountingposition at the chip mounting surface.

A functional element may be formed on at least any one of the wiringlayer formation surface and the wiring layer.

According to a second aspect of the present invention, the presentinvention provides a wiring substrate which mounts a semiconductor chipwith Flip-Chip, wherein the wiring substrate comprising: a basesubstrate; a wiring layer having an insulating layer and a wiring formedon a wiring layer formation surface which is one surface of the basesubstrate; an electrode formed on a chip mounting surface which is abackside of the wiring layer formation surface of the base substrate;and a through-electrode formed on the base substrate electricallyconnecting the wiring layer formed on the wiring layer formation surfaceand the electrode formed on the chip mounting surface, wherein a thermalexpansion coefficient of the base substrate is equal to a thermalexpansion coefficient of the semiconductor chip, or less than a thermalexpansion coefficient of the wiring layer. It is favorable that thethermal expansion coefficient of the semiconductor chip is smaller thanthat of the wiring layer.

With the present configuration, the above-described advantages areobtained for the semiconductor apparatus according to the first aspectof the present invention.

A material of the base substrate may be composed of any one of asilicon, a ceramic, and a photosensitive glass.

A reinforcing frame may be stuck at least on a part of outer part of thechip mounting position of the chip mounting surface. It is favorablethat a thermal expansion coefficient of the reinforcing frame is equalto that of the semiconductor chip, or less than that of the wiringlayer.

A thickness of the base substrate, at least one part of outer part ofthe semiconductor chip mounting position at the chip mounting surface,may be thicker than the other part of the semiconductor chip mountingposition at the chip mounting surface.

A functional element may be formed on at least any one of the wiringlayer formation surface and the wiring layer.

According to a third aspect of the present invention, the presentinvention provides a method for manufacturing a wiring substrate whichcomprises a base substrate and a wiring layer having an insulating layerand a wiring formed on a wiring layer formation surface, which is onesurface of the base substrate, and mounts a semiconductor chip withFlip-Chip, the method comprising steps of: forming a half-through-holefrom the wiring layer formation surface of the base substrate; forming afirst electrode on the wiring layer formation surface by burying thehalf-through-hole with an electrically conductive material; forming thewiring layer on wiring layer formation surface; and forming a secondelectrode for mounting the semiconductor chip by exposing thehalf-through-hole through thinning the base substrate from a backside ofthe wiring layer formation surface.

The method for manufacturing a wiring substrate may further comprise astep of thinning the base substrate by maintaining a step between atleast one part of outer part of a semiconductor chip mounting positionand other part of the semiconductor chip mounting position, by making awork amount smaller at least at the one part of outer part of thesemiconductor chip mounting position than the other part ofsemiconductor chip mounting position.

The method for manufacturing a wiring substrate may further comprise aprocess of forming a functional element at a process which forms thewiring layer.

According to a fourth aspect of the present invention, the presentinvention provides a method for manufacturing a wiring substrate whichcomprises a base substrate and a wiring layer formed on a wiring layerformation surface, which is one surface of the base substrate, andmounts a semiconductor chip with Flip-Chip, the method comprising stepsof: forming the wiring layer on wiring layer formation surface of thebase substrate; forming a through-hole which penetrates only the basesubstrate from a backside of the wiring layer formation surface of thebase substrate; forming an electrode for mounting the semiconductor chipat the backside of the wiring layer formation surface by burying thethrough-hole with an electrically conductive material.

The method for manufacturing a wiring substrate may further comprise astep of thinning the base substrate by keeping a step between at leastone part of outer part of a semiconductor chip mounting position and theother part of semiconductor chip mounting position, by making a workamount smaller at least at the one part of outer part of thesemiconductor chip mounting position than the other part ofsemiconductor chip mounting position.

The method for manufacturing a wiring substrate may further comprise aprocess of forming a functional element at a process which forms thewiring layer.

According to the aspects of the first to the fourth embodimentsexplained in the above, in the semiconductor apparatus, the wiringsubstrate, and the method for manufacturing the wiring substrate, sincethe semiconductor chip is bonded to the base substrate of the wiringsubstrate which has a thermal expansion coefficient close to that of thesemiconductor chip, an internal stress caused by mismatch of the thermalexpansion coefficient between them is substantially decreased. Inaddition, a change of an internal stress caused by mounting thesemiconductor apparatus on a motherboard and by temperature change underoperating circumstances is also decreased, thereby resulting in increasein the reliability. Accordingly, it becomes possible to overcome adecrease of allowance level of the internal stress due to, for example,growing in size of semiconductor chip according to increase in thenumber of external terminal, due to application of fragile Low-k film tothe interlayer dielectric film, and due to a decrease of stressrelaxation by using an environmentally-friendly lead-free solder.

In addition, since the wiring layer of the wiring substrate is formed ona rigid base substrate, it is suitable for forming a fine wiringpattern. Furthermore, since most of manufacturing processes of thesemiconductor apparatus can be implemented with a wafer, a highproduction efficiency is achieved, and thereby resulting in a low costmanufacturing.

Further, a stress is caused by the difference of thermal expansioncoefficient between the base substrate and a resin material used for theinterlayer dielectric film substantially occupying the wiring layer,which is formed at a backside of the chip mounting surface of the wiringsubstrate. However, by sticking a reinforcing frame partially orentirely to the outer part of the mounting position of the semiconductorchip at the chip mounting surface, the rigidity of the base substrate ismaintained even if the thickness of base substrate at the semiconductorchip mounting position is substantially thinned. As a result, it becomespossible to improve the mountability and the reliability by suppressingwarpage of the wiring substrate.

Moreover, a stress is caused by the difference of thermal expansioncoefficient between the base substrate and a resin material used for theinterlayer dielectric film substantially occupying the wiring layer,which is formed at a backside of the chip mounting surface of the wiringsubstrate. However, by increasing the thickness partially or entirely ofthe outer part of the mounting position of the semiconductor chip at thechip mounting surface, the rigidity of the base substrate is maintainedeven if the thickness of base substrate at semiconductor chip mountingposition is substantially thinned. As a result, it becomes possible toincrease the mountability and the reliability by suppressing warpage ofthe wiring substrate, as well as increasing simplicity of the process bysimultaneous formation of the surrounding step when the base substrateis thinned. Then, the cost can be down.

In addition, by disposing, for example, a capacitor, a resistor, and ainductor on the surface of base substrate for forming a wiring layer, orin the wiring layer, an optimum arrangement of functional elements, forexample, the capacitor, the resistor and the inductor, is achieved ateach optimum position in the wiring substrate. As a result, improvementsof high frequency characteristics and a high performance can beachieved. Shrinkage of the mounting area and an increase of designfreedom are also achieved.

Furthermore, by stacking the wiring layer on the base substrate whichhas a small thermal expansion coefficient and a high rigidity, itbecomes possible to form a fine wiring pattern compared with the casewhere the wiring layer is stacked on a resin-based base material.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view showing a structure of conventionalsemiconductor apparatus.

FIG. 2A is a cross sectional view showing a structure of first exampleof semiconductor apparatus in the first embodiment of the presentinvention.

FIG. 2B is a cross sectional view showing a structure of second exampleof semiconductor apparatus in the first embodiment of the presentinvention.

FIG. 2C is a cross sectional view showing a structure of third exampleof semiconductor apparatus in the first embodiment of the presentinvention.

FIG. 3A to 3F are cross sectional views of a wiring substrate at eachprocess of a method for manufacturing the wiring substrate of thesemiconductor apparatus in the first embodiment of the presentinvention.

FIG. 4 is a cross sectional view showing a structure of semiconductorapparatus in the second embodiment of the present invention.

FIG. 5A to 5E are cross sectional views of a wiring substrate at eachprocess of a method for manufacturing the wiring substrate of thesemiconductor apparatus in the third embodiment of the presentinvention.

FIG. 6 is a cross sectional view showing a structure of semiconductorapparatus in the fourth embodiment of the present invention.

FIG. 7A to 7D are cross sectional views of a semiconductor apparatus ateach assembly process after Flip-Chip bonding process of thesemiconductor apparatus in the fourth embodiment of the presentinvention.

PREFERRED EMBODIMENTS OF THE PRESENT INVENTION First Embodiment

Embodiments of the present invention will be explained in detail byreferring to figures. FIG. 2A is a cross sectional view showing astructure of a first example of a semiconductor apparatus in the firstembodiment of the present invention. FIG. 2B is a cross sectional viewshowing a structure of a second example of a semiconductor apparatus inthe first embodiment of the present invention. FIG. 2C is a crosssectional view showing a structure of a third example of a semiconductorapparatus in the first embodiment of the present invention. FIGS. 3A to3F are cross sectional views of a wiring substrate at each process of amethod for manufacturing the wiring substrate of the semiconductorapparatus in the first embodiment of the present invention.

In the first embodiment, as shown in FIG. 2A, a single or plural wiringlayers 5 is formed on one side of base substrate 3 which is composed ofsilicon as a wiring substrate 2, and on an electrode at the top layer ofwiring layer 5, bump 7 for external bonding is formed. In base substrate3, through-electrode 4 is formed for electrically connecting wiringsubstrate 5 and an electrode terminal on the other side of basesubstrate 3 on which wiring layer 5 is not formed (hereinafter, referredto as chip mounting surface). The electrode terminal on the chipmounting surface and semiconductor chip 1 are electrically andmechanically bonded with internal bonding bump 6 which is composed of,for example, Tin-Lead solder.

A thermal expansion coefficient of base substrate 3, which is composedof silicon, is substantially equal to that of semiconductor chip 1 andless than that of wiring layer 5. Then, a stress caused by thedifference of thermal expansion coefficient between semiconductor chip 1and base substrate 3 is substantially small. Therefore, as shown in FIG.2A, it is not always necessary to bury a space between semiconductorchip 1 and wiring substrate 2 with mold compound such as an epoxy-basedresin for partially supporting a bonding strength between them. As shownin FIG. 2B, it may be possible to bury the space between semiconductorchip 1 and wiring substrate 2 with mold compound 8 without puttingoverstress to the bonding part. It may also be possible, as shown inFIG. 2C, to bury only a perimeter of semiconductor chip 1 with moldcompound 8.

Next, a method for manufacturing the wiring substrate in a firstembodiment will be explained by referring to FIGS. 3A to 3F.

As shown in FIG. 3A, after forming a silicon oxide film (SiO2 film) ofinsulating layer 11 a on a silicon wafer of base substrate 3, insulatinglayer 11 a is bored by pattering a predetermined hole position withphotolithography. Then, a half-through-hole of 110 μm in depth is formedwith reactive ion etching (RIE). A diameter of the half-through-hole wasset at 80 μm. A distance between the holes was 150 μm. The RIE is amethod for removing the oxide through reactions of radical atom in thereactive gas plasma. It is possible to conduct anisotropic etching withRIE like dry etching.

Next, as shown in FIG. 3B, a TEOS (Si(OC2H5)4) film of insulating layer11 b is formed on a surface of the half-through-hole with plasma CVD,followed by a copper (Cu) film formation of a plating seed layer withsputtering. When a film is formed by CVD on whole surface of a holewhich has a substantially deep depth as the present structure, it isdifficult to form the film on a side wall of the hole due to a shape ofthe hole thereof. Therefore, the TEOS film, which has good step coveragefrom the beginning of film formation, was selected as insulating layer11 b. After that, the half-through-hole was filled with conductor 12 ofCu with plating of a damascene method, and chemical-mechanical polished(CMP) for planarization of conductor 12. Other than the damascenemethod, a method filling the conductor with CVD is also possible. Otherthan the metal, an electrically conductive resin may also be usable forthe conductor.

Next, as shown in FIG. 3C, after patterning the CMP treated Cu film atupper layer with etching, wiring layer 5 is formed with a buildup methodfor forming a multilayer wiring layer by sequentially repeatingformation of interlayer dielectric film 14, formation of a via hole,desmear treatment, and formation of wiring 13. In FIG. 3C, an example ofwiring layer with three levels is shown, but not limited to threelevels.

An increase in operation speed can be expected by fabricating functionalapparatus, for example, a capacitor, a resistor, and an inductor duringformation of wiring layer 5. For example, a decoupling capacitorfunction can be obtained by inserting a parallel plate capacitor formedby sandwiching ferroelectric material, which is formed as a part ofinterlayer dielectric film 14, with a power line and a ground linewithin wiring layer 5. After that, the surface is covered with solderresist, such as polyimide, except electrode 16 a of the top wiringlayer. Then, a structure at an external bonding bump side is completed.

Functional elements, for example, a capacitor, a resistor, and aninductor are fabricated in wiring layer 5. It is possible to apply aconventional semiconductor diffusion process for fabricating thefunctional elements since they are formed on a silicon which is able toform a functional element such as a capacitor by applying a thin filmprocess on the silicon substrate, which has a via buried with conductivematerial. Therefore, it is possible to achieve a manufacturing line withprecise manufacturing and low cost production, for example, throughsuppressed investment.

Next, as shown in FIG. 3D, for protecting a surface at a wiring layerformation side, the surface is covered with support 17 before a thinningtreatment of silicon. After turning over the silicon wafer, the siliconis thinned from about 700 μm to about 200 μm with mechanical grinding.Then, the silicon is further thinned to about 100 μm with RIE forexposing the half-through-hole.

In the first embodiment, a combination of mechanical grinding and RIEhas been employed for the thinning considering the manufacturing costand the manufacturing efficiency. After the mechanical grinding, astrained layer is formed at the surface in general. A micro-crack isalso formed in some case. Since there is a possibility that thesedecrease the reliability, a careful consideration for conditions, forexample, on removal rate of the mechanical grinding and the chasingspeed, is required. The thinning process can be achieved with onlymechanical grinding if it does not effect on the reliability.

Next as shown in FIG. 3E, after RIE treatment, a step appears due to thedifference of etching rate caused by the difference of material betweenthe through-electrode area and the other area. After that, the cupper isexposed by entirely removing insulating layer 11 b with CMP as well asplanarizing the RIE treated surface. Then, a SiO2 film of insulatinglayer 11 c is formed on the surface, and patterning is conducted on thefilm with photolithography.

Finally, as shown in FIG. 3F, after forming a second electrode 16 b onthe opening area of insulating layer 11 c, cover film 18 of siliconnitride film (SiN film) is formed. After that, by removing support 17,the wiring substrate is completed. In the first embodiment, SiO2 and SiNhave been used for the insulating layers 11 a, 11 b, 11 c, and coverfilm 18. However, other than the above materials, SiC, SiOF, and SiOCformed with plasma CVD, which is capable of forming a film atsubstantially low temperature, can also be used for the film.

Semiconductor chip 1 is mounted with face-down on wafer shaped wiringsubstrate 2 which was manufactured through processes shown in FIGS. 3Ato 3F. After reinforcing semiconductor chip 1 with mold compound 8appropriately, semiconductor chip 1 is separated individually, andexternal bonding bump 7 is formed to complete a semiconductor apparatus.In this manufacturing process, since the wafer shape is maintained untilclose to the final process, the manufacturing efficiency is high andmanufacturing and inspection costs can be cut down.

When a chip size of semiconductor chip 1 is over 10×10 mm and the numberof external output pin is over 1000, wiring substrate 2 becomes large,such as 40˜50 mm. In this case, the thinned silicon substrate has not asufficient mechanical strength. Then, there may be a possibility tobreak wiring substrate 2 during the separation of the chip individually.Therefore, it is favorable to cut wiring substrate 2 after backing up itby taping with stiffener 9 before cutting wiring substrate 2, afterthinning the silicon and forming a bonding electrode of thesemiconductor chip. In addition, if manufacturing of the wiringsubstrate and mounting of semiconductor chip can be implementedsequentially, it is favorable to mount semiconductor chip 1 on thewiring substrate as a wafer, and after that, to implement the separationprocess.

In the present invention, a material, which is able to relax thedifference of thermal expansion between a supporting substrateexemplified by a motherboard and the wiring substrate, may be used forthe insulating layer. It is favorable that the material is selectedconsidering expansion coefficients of the supporting substrate and thebase substrate. Optimally, an expansion coefficient of the material forthe insulating layer is smaller than that of the supporting substrate,and larger than that of the base substrate.

In the first embodiment, silicon is used for semiconductor chip 1 andbase substrate 3 of wiring substrate 2, but not limited to the silicon.For base substrate 3, a material, of which thermal expansion coefficientis equal to that of semiconductor chip 1 or smaller than that of wiringlayer 5, is used. Other than the silicon, for example, ceramics or aphotosensitive glass which is able to form a fine hole can be used. Ifthe photosensitive glass is selected as base substrate 3, a through-holeis formed first instead of the half-through-hole. After that, anelectrically conductive treatment for both sides of the glass plate anda wiring layer formation are conducted. Practically, by putting a maskwhich has a pattern for forming a hole on the photosensitive glass, anexposure process with a violet light which includes a predeterminedspectrum, and a development process with a heat treatment are conducted.Then, a crystallized part is removed with acid to form base substrate 3having a through-hole.

Second Embodiment

FIG. 4 is a cross sectional view showing a structure of semiconductorapparatus in the second embodiment of the present invention. In thesecond embodiment, in addition to the configuration of the firstembodiment, a stiffener 9 of reinforcing frame is stuck at around amounting surface area of semiconductor chip 1 on base substrate 3 forincreasing rigidity of wiring substrate 2. Since the rigidity of wiringsubstrate 2 can be increased with stiffener 9, it is possible to thinthe thickness of a package by thinning base substrate 3, and to providecountermeasures for increasing cooling performance against the increaseof power consumption and heat generation of semiconductor chip 1 byattaching heat sink 10 at the bottom of semiconductor chip 1 usingstiffener 9. It is also favorable that a thermal expansion coefficientof stiffener 9 is equal to that of semiconductor chip 1, or less thanthat of wiring layer 5, as well as the case of base substrate 3.

Third Embodiment

FIG. 5A to 5E are cross sectional views of a wiring substrate at eachprocess of a method for manufacturing a wiring substrate of asemiconductor apparatus in a third embodiment of the present invention.

In the first embodiment, wiring layer 5 is formed after forming ahalf-through-hole in base substrate 3, and burying the half-through-holewith an electrically conductive material. However, in the thirdembodiment, after forming wiring layer 5 first on base substrate 3,wiring substrate 2 is completed by forming a through-electrode and abackside electrode

First, as shown in FIG. 5A, insulating layer 11 a and wiring layer 5 areformed on base substrate 3 of silicon having a thickness of 700 μm withthe same manufacturing method as the first embodiment.

After protecting a surface of wiring layer 5 with support 17, the waferis turned over and base substrate 3 is thinned to 180 μm from backsidewith mechanical grinding. Then, a central part of base substrate 3 isthinned to 80 μm with RIE. Although not shown since FIG. 4 is anenlarged illustration, when RIE is conducted, a width of 8.5 mm atperipheral area of the substrate is masked. Accordingly, a step isformed on the surface by further thinning of the central area with RIE.With the above, a thickness of the through-electrode area can be furtherthinned, while maintaining rigidity of base substrate 3. In thisembodiment, an outside dimension of wiring substrate 2 is 30×30 mm, anoutside dimension and a thickness of semiconductor chip 1 are 10×10 mmand 700 μm, respectively. In this embodiment, the though-hole part andits surrounding are unified with the same material. However, as with thesecond embodiment, the rigidity is secured by sticking stiffener 9around a smooth surface of wiring substrate 2.

Next, as shown in FIG. 5B, after forming SiO2 film of insulating layer11 c on a silicon wafer of base substrate 3, insulating layer 11 c isbored after pattering a predetermined hole position withphotolithography, and a through-hole is formed with RIE for exposing awiring at the bottom of wiring layer 5. After that, a side wall and anupper surface of the through-hole are insulated with insulating layer 11c of TEOS film.

Then, the through-hole is filled with a conductor 12 of Cu with adamoscene method, and chemical-mechanical polished (CMP) forplanarization. After that, as shown in FIG. 5D, electrode 16 b isformed, and as shown in FIG. 5E, SiN cover film 18 is formed.Accordingly, a wafer shaped wiring substrate 2 is completed.

Fourth Embodiment

FIG. 6 is a cross sectional view showing a structure of a semiconductorapparatus in a fourth embodiment of the present invention. FIGS. 7A to7D are cross sectional views of a semiconductor apparatus at an assemblyprocess after Flip-Chip bonding process of the semiconductor apparatusin the fourth embodiment of the present invention.

In the fourth embodiment, according to FIG. 6, a central area is thinnedby forming a step around base substrate 3. The back side of basesubstrate 3 is ground after mounting and molding semiconductor chip 1with mold compound to achieve a thin semiconductor apparatus in total.

First, as shown in FIG. 7A, semiconductor chip 1 is bonded withFlip-Chip bonding to a wafer shaped wiring substrate 2, to which support17 is stuck. Then, as shown FIG. 7B, mold compound 8 is filled in aspace between semiconductor 1 and base substrate 3. Mold compound 8 issupplied until the surface of the molded substance is covered with moldcompound 8. This is implemented for the purpose of decreasing an effectof damage caused by grinding of the backside of semiconductor chip 1. Itis possible to neglect the process, or to change a supply quantity ofmold compound 8 arbitrarily if it does not effect on the bonding portionand the apparatus reliability.

After that, as shown in FIG. 7C, the backside of semiconductor chip 1 isground until the thickness becomes about 50 μm. The thickness of thesemiconductor apparatus except an external bonding bump is set at about220 μm. Meanwhile, wiring layer 5 is consist of two layers. Next, asshown in FIG. 7D, the wafer is diced into chips, and support 17 ispeeled off. Finally, the external bonding bump is formed with a microball mounting method to complete the semiconductor apparatus. Forexample, a solder paste printing method, an evaporation method, anelectrolytic plating and others may be used for forming the externalbonding bump. The order of peeling off of the support and the dicingprocess is arbitrarily changed considering the bump formation method andproduction efficiency.

Fifth Embodiment

In the first embodiment, after forming a through-electrode on the basesubstrate of silicon, a wiring layer is formed and bonded to a support.Then, the silicon is thinned to expose a mounting surface ofsemiconductor chip 1 to form wiring substrate 2. In the thirdembodiment, wiring layer 5 is formed on the silicon substrate, and thesilicon is thinned from the backside of it. After that, by forming athrough-electrode, a mounting surface of semiconductor chip 1 is formedto form wiring substrate 2.

In either case, the mounting surface of semiconductor chip 1 is formedat a final process. In a fifth embodiment, a via, which is athough-hole, is formed on base substrate 2 with RIE, followed byformation of an insulating film on the inner wall, filling of aconductor, and planarization with CMP to form a pad for mountingsemiconductor chip 1. Then, the pad surface is bonded to a support,followed by arbitrary combination of grinding and RIE to thin thesilicon to form a through-electrode. After that, a multi wiring layerand an external terminal are formed to form a wiring substrate.According to this method, a diffusion process technology ofsemiconductor manufacturing can be applied to, for example, an electrodeformation process on a mounting surface of semiconductor chip 1 and afunctional element formation process such as a capacitor, which are bothrequired substantially high accuracy, before forming the support andmulti wiring layer.

In these embodiments, a diameter of the via is set at 80 μm. However, adiameter of 150 μm at boring process for forming the via is acceptable.Even though depending on an alignment pitch of electrodes, a smaller viais favorable from high density point of view. Then, a diameter less than50 μm is employed. A diameter of 10 μm is achievable by selecting a viaformation method.

In the process for exposing a via, when the silicon and the conductorfilled in the via are processed together with mechanical grounding, thegrinding stone is likely to be clogged with the conductor, therebyresulting in rough surface. As a result, the process yield may bedecreased. Therefore, it is favorable that a percentage of a via surfacewithin the silicon surface, where is to be ground, is less than 2%.Because of this reason, when extraction of 60 substrates with 4000 pinsfrom 8 inch wafer is layouted, a diameter less than 30 μm is the mostsuitable for the through-via. However, considering a filling efficiencyof the conductive material in the via from filling process point ofview, a diameter more than 10 μm is favorable.

As explained in the above, according to the present embodiment, sincesemiconductor chip 1 is bonded to base substrate 3 of wiring substrate 2which has a thermal expansion coefficient close to that of semiconductorchip 1, an internal stress caused by mismatch of the thermal expansioncoefficient between them is substantially decreased. In addition, achange of internal stress caused by mounting a semiconductor apparatuson a motherboard and by temperature change under operating circumstancesis also decreased, thereby resulting in increase in reliability.Accordingly, it becomes possible to overcome a decrease of allowancelevel of the internal stress due to, for instance, growing in size ofsemiconductor chip 1 according to increase of the number of externalterminal, application of fragile Low-k film to an interlayer dielectricfilm, and decrease of stress relaxation ability by using anenvironmentally-friendly Lead-free solder.

In addition, according to the present embodiment, since wiring layer 5of wiring substrate 2 is formed on a rigid base substrate 3, it issuitable to form a fine wiring pattern, and most of the manufacturingprocesses of the semiconductor apparatus can be processed with a wafer.As a result, a high production efficiency and a low cost manufacturingare both can be achieved.

Further, according to the present embodiment, a stress is caused by thedifference of thermal expansion coefficient between the base substrateand a resin material used for the interlayer dielectric filmsubstantially occupying wiring layer 5, which is formed at backside ofthe chip mounting surface of wiring substrate 2. However, by sticking areinforcing frame partially or entirely to the outer part of a mountingposition of semiconductor chip 1 at the chip mounting surface, therigidity of base substrate 3 is maintained even if the thickness of basesubstrate 3 at the mounting position of semiconductor chip 1 issubstantially thinned. Accordingly, it is possible to increase amountability and a reliability by suppressing warpage of wiringsubstrate 2.

Moreover, according to the present embodiment, a stress is caused by thedifference of thermal expansion coefficient between base substrate 3 anda resin material used for the interlayer dielectric film substantiallyoccupying wiring layer 5, which is formed at backside of a chip mountingsurface of wiring substrate 2. However, by increasing the thicknesspartially or entirely of the outer part of the mounting position ofsemiconductor chip 1 at the chip mounting surface, the rigidity of basesubstrate 3 is maintained even if the thickness of base substrate 3 atthe mounting position of semiconductor chip 1 is substantially thinned.As a result, it is possible to increase the mountability and thereliability by suppressing warpage of wiring substrate 2, as well asincreasing simplicity of the process by simultaneously forming asurrounding step when base substrate 3 is thinned. Accordingly, the costcan be down.

In addition, according to the present embodiment, by disposing, forexample, a capacitor, a resistor, and a inductor on the surface of basesubstrate 3 for forming a wiring layer, or in wiring layer 5, an optimumarrangement of functional elements, for example, the capacitor, theresistor and the inductor is achieved at optimum position in wiringsubstrate 5 for each element. As a result, improvements of highfrequency characteristics and high functionality can be achieved.Moreover, shrinkage of mounting area and increase of design freedom canbe realized.

Furthermore, according to the present embodiment, by stacking wiringlayer 5 on base substrate 3 which has a small thermal expansioncoefficient and high rigidity, it becomes possible to form a fine wiringpattern compared with the case where wiring layer 5 is stacked on aresin-based base material.

It is obvious that the present invention is not limited to eachembodiment, and the each embodiment may be changed within atechnological scope and sprit of the present invention. In addition, thenumber of components, positions, features, and the like are not limitedto the embodiment, and they may be determined based on a practicalapplication of the present invention.

The identical elements at each figure are given the same symbols.

POSSIBILITY FOR INDUSTRIAL APPLICATION

A semiconductor apparatus, a wiring substrate for the semiconductorapparatus, and a method for manufacturing the wiring substrate accordingto the present invention are applicable to all semiconductor apparatusesand not limited the possibility of application, if the semiconductorapparatus is such that a semiconductor chip is mounted on a wiringsubstrate with Flip-Chip method.

While the present invention has been described by associating with somepreferred embodiments and examples, it is to be understood that theseembodiments and examples are merely for illustrative of the invention byan example, and not restrictive. While it will be obvious to thoseskilled in the art that various changes and substitutions by equivalentcomponents and techniques are eased upon reading the specification, itis believed obvious that such changes and substitutions fit into thetrue scope and spirit

1. A semiconductor apparatus in which a semiconductor chip is mounted ona wiring substrate with Flip-Chip, wherein the wiring substratecomprises: a monolithic base substrate formed from any one of a silicon,a ceramic, or a photosensitive glass; a wiring layer having aninsulating layer and a wiring formed on a wiring layer formation surfacewhich is one surface of the monolithic base substrate; an electrodeformed on a chip mounting surface which is a backside of the wiringlayer formation surface of the monolithic base substrate; and athrough-electrode formed on the monolithic base substrate electricallyconnecting the wiring layer formed on the wiring layer formation surfaceand the electrode formed on the chip mounting surface, wherein a thermalexpansion coefficient of the monolithic base substrate is equal to athermal expansion coefficient of the semiconductor chip, and the thermalexpansion coefficient of the monolithic base substrate is less than athermal expansion coefficient of the wiring layer, wherein thesemiconductor chip is bonded to the chip mounting surface withface-down.
 2. The semiconductor apparatus according to claim 1, whereina reinforcing frame is stuck at least on a part of an outer part of achip mounting position of the chip mounting surface.
 3. Thesemiconductor apparatus according to claim 2, wherein a thermalexpansion coefficient of the reinforcing frame is equal to the thermalexpansion coefficient of the semiconductor chip, or less than thethermal expansion coefficient of the wiring layer.
 4. The semiconductorapparatus according to claim 1, wherein a thickness of the monolithicbase substrate, at least a part of an outer part of a semiconductor chipmounting position at the chip mounting surface, is thicker than thesemiconductor chip mounting position at the chip mounting surface. 5.The semiconductor apparatus according to claim 1, wherein a functionalelement is formed on at least any one of the wiring layer formationsurface or the wiring layer.
 6. The semiconductor apparatus according toclaim 1, wherein the thermal expansion coefficient of the semiconductorchip is smaller than a thermal expansion coefficient of the wiringlayer.
 7. A wiring substrate which mounts a semiconductor chip withFlip-Chip, wherein the wiring substrate comprises: a monolithic basesubstrate formed from any one of a silicon, a ceramic, or aphotosensitive glass; a wiring layer having an insulating layer and awiring formed on a wiring layer formation surface which is one surfaceof the monolithic base substrate; an electrode formed on a chip mountingsurface which is a backside of the wiring layer formation surface of themonolithic base substrate; and a through-electrode formed on themonolithic base substrate electrically connecting the wiring layerformed on the wiring layer formation surface and the electrode formed onthe chip mounting surface, wherein a thermal expansion coefficient ofthe monolithic base substrate is equal to a thermal expansioncoefficient of the semiconductor chip, and the thermal expansioncoefficient of the monolithic base substrate is less than a thermalexpansion coefficient of the wiring layer.
 8. The wiring substrateaccording to claim 7, wherein a reinforcing frame is stuck at least on apart of an outer part of a chip mounting position of the chip mountingsurface.
 9. The wiring substrate according to claim 8, wherein a thermalexpansion coefficient of the reinforcing frame is equal to the thermalexpansion coefficient of the semiconductor chip, or less than thethermal expansion coefficient of the wiring layer.
 10. The wiringsubstrate according to claim 7, wherein a thickness of the monolithicbase substrate, at least a part of an outer part of a semiconductor chipmounting position at the chip mounting surface, is thicker than thesemiconductor chip mounting position at the chip mounting surface. 11.The wiring substrate according to claim 7, wherein a functional elementis formed on at least any one of the wiring layer formation surface orthe wiring layer.
 12. The wiring substrate according to claim 7, whereinthe thermal expansion coefficient of the semiconductor chip is smallerthan a thermal expansion coefficient of the wiring layer.
 13. A methodfor manufacturing a wiring substrate which comprises a monolithic basesubstrate formed from any one of a silicon, a ceramic, or aphotosensitive glass and a wiring layer having an insulating layer and awiring formed on a wiring layer formation surface, which is one surfaceof the monolithic base substrate, and mounts a semiconductor chip withFlip-Chip, and a thermal expansion coefficient of the monolithic basesubstrate is equal to a thermal expansion coefficient of thesemiconductor chip, and the thermal expansion coefficient of themonolithic base substrate is less than a thermal expansion coefficientof the wiring layer, the method comprising steps of: forming ahalf-through-hole from the wiring layer formation surface of themonolithic base substrate; forming a first electrode on the wiring layerformation surface by burying the half-through-hole with an electricallyconductive material; forming the wiring layer on the wiring layerformation surface; and forming a second electrode for mounting thesemiconductor chip by exposing the half-through-hole through thinningthe monolithic base substrate from a backside of the wiring layerformation surface.
 14. The method for manufacturing a wiring substrateaccording to claim 13, further comprising a step of: thinning themonolithic base substrate by maintaining a step between at least onepart of an outer part of a semiconductor chip mounting position and theother part of the semiconductor chip mounting position, by making a workamount smaller at least at the one part of the outer part of thesemiconductor chip mounting position than the other part of thesemiconductor chip mounting position.
 15. The method for manufacturing awiring substrate according to claim 13, further comprising a step of:forming a functional element during forming the wiring layer.
 16. Amethod for manufacturing a wiring substrate which comprises a monolithicbase substrate formed from any one of a silicon, a ceramic, or aphotosensitive glass and a wiring layer formed on a wiring layerformation surface, which is one surface of the monolithic basesubstrate, and mounts a semiconductor chip with Flip-Chip, and a thermalexpansion coefficient of the monolithic base substrate is equal to athermal expansion coefficient of the semiconductor chip, and the thermalexpansion coefficient of the monolithic base substrate is less than athermal expansion coefficient of the wiring layer, the method comprisingsteps of: forming the wiring layer on the wiring layer formation surfaceof the monolithic base substrate; forming a through-hole whichpenetrates only the monolithic base substrate from a backside of thewiring layer formation surface of the monolithic base substrate; andforming an electrode for mounting the semiconductor chip at the backsideof the wiring layer formation surface by burying the through-hole withan electrically conductive material.
 17. The method for manufacturing awiring substrate according to claim 16, further comprising a step of:thinning the monolithic base substrate by maintaining a step between atleast one part of an outer part of a semiconductor chip mountingposition and an other part of the semiconductor chip mounting position,by making a work amount smaller at least at the one part of the outerpart of the semiconductor chip mounting position than the other part ofthe semiconductor chip mounting position.
 18. The method formanufacturing a wiring substrate according to claim 16, furthercomprising a step of: forming a functional element during forming thewiring layer.